1. Field of the Invention
This invention relates to a circuit and a method for providing an override voltage to control gates through boosting of a selected word line for TWIN metal oxide nitride oxide MONOS semiconductor memory.
More particularly this invention relates to providing a means of using capacitive coupling between selected word lines and neighboring control gates to boost the voltage for the program, erase or read modes of MONOS memory.
2. Description of Related Art
High density flash memory arrays have been described in previous patents.
U.S. Pat. No. 6,011,725 (Eitan) xe2x80x9cTwo Bit Non-volatile Electrically Erasable and Programmable Semiconductor Memory Cell Utilizing Asymmetrical Charge Trappingxe2x80x9d describes a memory cell which uses charge trapping within various layers of the memory cell cross-section to store information. A single word gate has an underlying single oxide-nitride-oxide (ONO) composite layer in which electrons are trapped at two separate locations within the nitride layer. Thus, two hard bits of data can be stored under a single word gate, which roughly doubles the cell density.
The features of Twin MONOS memory cell structures distinctive of other flash and MONOS EEPROM cells, has been documented in U.S. Pat. No. 6,255,166 B1, xe2x80x9cNonvolatile memory cell, method of programming the same and nonvolatile memory arrayxe2x80x9d, by S. Ogura, et. al, and U.S. patent application Ser. No. 09/810122, xe2x80x9cArray architecture of nonvolatile memory and operation methodxe2x80x9d, by Y. Hayashi, et. al., submitted on Mar. 19, 2001. FIG. 1 gives a cross-section of a Twin MONOS memory array. A single memory cell CELL[x] is composed of a control gate CG[x], a bit diffusion junction BL[x] and two halves of a word gate. In particular, the 2-bit nature of a cell is allowed through its structure composed of two separate nitride layers ML, MR residing in the oxide under two control gate components CG_L and CG_R, respectively. The side wall polysilicon control gates CG_L and CG_R may be physically or electrically connected to form the shared control gate CG[x] polysilicon. The bit diffusion BL[x] lies beneath the oxide under the control gate CG[x]. The 2-bit nature of a cell can be realized by selecting the left or right side of a selected cell through application of specific voltages to the control gates, bit line diffusions and word gates of the selected cell and the neighbor cells. The control gate lines are unique to the twin MONOS structure and provide an extra degree of control in choosing between the left or right side of the selected cell. However, the control gate lines also require additional decoding circuitry compared to other types of dual bit cells. Appropriate voltages need to be applied to the selected control gate CGs, as well as to an override neighbor CGo. In order to select one memory storage site, it is necessary to mask the threshold of the neighboring memory storage site by an override voltage. This voltage is usually higher than that of the voltage applied to the selected control gate CGs during read. For technologies with power supplies of 1.8V and below, the override voltage VCGo is usually higher than the power supply voltage, typically in a range of 2.5 to 3.0V. If for read or program operations, cell[X] is selected, then the corresponding control gate CGs is selected. When a memory site is targeted, then the word line adjacent to the side is also selected as WLs, and the control gate CGo on the other side of the word line is applied an override voltage VCGo.
An example of a Twin MONOS bit diffusion array is given with array version A in FIG. 1 and FIG. 2, based on U.S. Pat. No. 6,255,166 B1. This array consists of a plurality of memory cells, a plurality of word-lines 110, control gate-lines 130, and bit-lines 180 connected to the cells. One word line (WL) connects a row of N cells, the word line polysilicon connected throughout the entire word line, over and between the control gate polysilicon lines. In FIGS. 1 and 2, there are M control gate lines 130, 220 equal to the number of bit-lines, both of which are parallel to each other and perpendicular to the word lines. During any read, program, or erase mode, one in every Y cells on one WL is selected. Therefore, CG drivers and CG decoders for selecting one in every Y control gate line are connected to the memory matrix, along with BL drivers and BL decoders for selecting one in every Y bit line. WL driver and WL decoders are also connected to the matrix, which provide the correct voltages to the memory word lines for selection of one WL. Referring to FIG. 1, when MR of Cell[X] is targeted, WL is selected, CG[x] is the selected CGs, and CG[x+1] is the override CGo.
Based on U.S. patent application Ser. No. 09/810122, another array version B is described in FIGS. 3 and 4. The relationship between the rows of word lines 310, 430 and vertical bit line columns remains the same. However, in this metal bit array type, the control lines also run in parallel to the word lines, instead of the bit lines as in the diffusion bit array type Version A. Referring to FIG. 3, when MR of Cell[x] is targeted, then WL[x] is the selected word line WLs, CG[x] is the selected control gate line CGs and CG[x+1] is the override control gate line CGo. In Version A and B, one WL is selected during program and read. Also in both versions A and B, the decoders for the bit lines may be constructed so that one out of Y bit-lines are selected at the same time for 1 out of Y cells to be selected. In Version A however, for one out Y cells to be selected, the corresponding 1 out of Y control-lines need to be selected in a decoder scheme similar to the bit line""s. The Version B control gate decoder is different than Version A in that only one control gate line 420 is selected with the one word line 430, with additionally only one override neighbor control gate line.
The timing to setup the voltages on targeted WL, BL, and CG in a memory matrix is of particular importance to memory performance, especially during read. Load capacitance and resistance on the lines contribute to significant delays in switching between voltage states. The main control gate lines, and word gate lines are poly gates of cells connected together which have significant resistance and capacitance, depending on the length of the array. In FIG. 4, one main bit line 480 connects an entire column of cells through the diffusion, which also carries a significant capacitance and resistance. The resistance of the bit line is generally decreased by strapping/stitching the diffusion line at intervals to a metal bit line. However, in order to achieve high density and low cost, additional metal lines for both the word and control gate poly lines are not always feasible. Therefore, the voltage set up time is defined by the slowest line. The slowest delay is usually determined by the control gate line, which is very narrow and is difficult to silicide.
Conventionally, the voltage setup time for high performance read is reduced by decreasing the capacitance of the lines, thereby decreasing the charge up time. The capacitance for any of the lines can be cut with the addition of select transistors to the lines in question, creating sub-blocks within the memory matrix and decreasing the loads for the driver and decoders for the line. For example with matrix version A, to reduce the total bit line capacitance, a main bit line can be connected to sub bit lines via select gates. Thus the cell diffusion capacitance can be reduced to that of only one sub block in the memory matrix. The same concept of sub-blocking and select transistors may be similarly applied to the control gate lines and word gate lines. However, some penalties of the select gates are larger layout area, and additional concerns about sub block lines floating when unselected, and the select transistor size having sufficient driveability for a line.
With or without select transistors, the sizes of the width of pass transistors throughout the drivers and decoders may be increased to minimize delays, but this also results in the penalty of larger layout, as well as parasitic switching current through the decoders to the voltage sources in the drivers. These voltages may be through a power supply with a considerable leakage current tolerance, but if power consumption is a vital concern such as when voltages are produced internally on a chip such as through charge pumps, then large current consumption through switching must be a consideration.
The penalties of larger switching current and layout area that come with larger pass transistor widths within the driver and decode circuits are weighed against the benefit of faster switching of voltage conditions. The set up of voltage conditions from unselected cell to selected or override cell voltages is a concern for memory performance during all of the read, program, and erase modes. Transistor sizing through the decoders however, should still be optimized for the mode where fast timing for passing voltages through the decoder is most critical, which in most cases is read. However during read, the voltage differences between selected and neighbor (or override) cells to unselected cells conditions is less extreme than that of program, and so with low driveability, the pass transistors need to be larger. If however, selected and override voltages can be applied to the correct lines without being actively passed through the decoders during read, then transistor sizing could be reduced, and optimized for the program and erase modes, in which not only is driveability higher, but set up speed is less critical.
It is the objective of this invention to provide a circuit and semiconductor method to take advantage of control gate-word line, CG-WL capacitance coupling for using a selected word line to boost a precharged and floating neighbor control gate line voltage.
It is further an objective of this invention to avoid using voltage switching via the control gate decoders, but to use the capacitance coupling mentioned above.
It is further an objective of this invention to vary the boosted control gate voltage through the booster word line voltage and the precharged starting voltage for the boosted control gate.
It is yet another objective of this invention to provide a means of faster voltage setup on the control gate line by a combination of boosting and voltage switching.
It is yet another objective of this invention to increase the capacitance coupling ratio by boosting a single control gate line with two word gate lines.
It is another objective of this invention to reduce the boosting effect in the selected control gate line by stepping down the voltage of a third word gate.
It is still a further objective of this invention to provide another array organization in which the left and right sidewall control gate components are separated lines.
It is another objective of this invention to provide a method of using the separated CG line organization in order to increase the boosting capacitance.
It is yet another objective of this invention to provide a means of organizing even memory cells into a bank separate from odd memory cells grouped to another bank, so that control gate voltages need not switch between successive reads within a bank.
In the earlier matrix scheme for TWIN MONOS version A, a decoder and driver for control gates and a decoder and driver for bit lines were required to pass the select, override neighbor, and unselect voltage conditions on the memory cells for all modes of read, program, and erase. Decoders and drivers for the WL, BL, and CG could be used to pass the correct voltages to the matrix in version B, but the structure characteristic of version B allows an alternative to passing voltages through the decoders of the CG or WL.
Because the poly control gate lines 420, 440 are parallel to the poly word lines 430 in Version B, there is a significant capacitance between word lines and control gate lines. The selected word line 430 is always positioned between the selected control gate 420 line and the override neighbor control gate line 440 during read and program modes. Line capacitance assumptions are made for the purposes of this explanation, based on detailed calculations and simulations. The capacitance between a poly word line and an adjacent poly control gate is defined as CCG-WL, and is depicted with other control gate capacitances in FIG. 7. About 55% of a total control gate capacitance CCG is between the CG and the two adjacent WL""s(2*CCG-WL), and 70% of the total WL capacitance CWL is between the WL and both adjacent control gates (2*CCG-WL). The coupling capacitance CCG-WL provides a boost capacitance CCGO-WLS between the boosted CGo and a selected WLs. By using a selected word line 430 to boost a pre-charged and floating neighbor control gate line 440, the voltage of the override control gate can be setup faster than by voltage switching of CGo through decoders. Also, by utilizing boosting instead of voltage switching for the override voltage, charge pumps do not need to provide high voltages during read.
(It should be noted that by similarly switching the selected or override control gates, a floating word line voltage may be boosted. But usually the control gate line delay is significantly higher than the word line delay, so no access time improvement is gained)
Although the control gate line has a higher RC delay compared to the word line, word line to control gate line coupling charges up the control gate line within the faster word line RC delay. The time required for the control gate line 440 to be boosted up to the override voltage is the same time it takes for the booster word line 430 to switch from a precharged voltage to the booster voltage. Assuming that the word line 430 switching through the decoders is faster than control line 440 switching through decoders, then capacitance boosting of the control gate is faster than charging through the control gate decoders. In this scheme, the fastest decoder transistor sizes to be optimized for read are those in the word line decoders. Fortunately, the word line decoder is usually composed of low voltage logic. Boosting a precharged control line not only decreases switching set up time and reduces decoder layout area, but also reduces some other problem considerations of the driver/decoder pass transistors mentioned earlier in the prior art section. Boosting a precharged voltage eliminates the need of a voltage source/chargepump to provide the boosted up control gate voltage, and the large switching current through the control gate driver and decoder from said voltage source.
In considering the capacitance boosting of a voltage, it should be noted that the boosted voltage is dependent on capacitance between the WL and CG represented by CCG-WL, the total parasitic load capacitance on the boosted line (here CCG), as well as the booster switching voltage (here VWL).